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| INTEGRATED CIRCUITS DATA SHEET For a complete data sheet, please also download: * The IC04 LOCMOS HE4000B Logic Family Specifications HEF, HEC * The IC04 LOCMOS HE4000B Logic Package Outlines/Information HEF, HEC HEF4043B MSI Quadruple R/S latch with 3-state outputs Product specification File under Integrated Circuits, IC04 January 1995 Philips Semiconductors Product specification Quadruple R/S latch with 3-state outputs DESCRIPTION The HEF4043B is a quadruple R/S latch with 3-state outputs with a common output enable input (EO). Each latch has an active HIGH set input (S0 to S3), an active HIGH reset input (R0 to R3) and an active HIGH 3-state output (O0 to O3). When EO is HIGH, the state of the latch output (On) can be determined from the function table below. When EO is LOW, the latch outputs are in the high impedance OFF-state. EO does not affect the state of the latch. HEF4043B MSI Fig.2 Pinning diagram. The high impedance off-state feature allows common busing of the outputs. HEF4043BP(N): HEF4043BD(F): HEF4043BT(D): 16-lead DIL; plastic (SOT38-1) 16-lead DIL; ceramic (cerdip) (SOT74) 16-lead SO; plastic (SOT109-1) ( ): Package Designator North America PINNING EO S0 to S3 R0 to R3 O0 to O3 common output enable input set inputs (active HIGH) reset inputs (active HIGH) 3-state buffered latch outputs FUNCTION TABLE INPUTS EO L H H H Notes 1. H = HIGH state (the more positive voltage) L = LOW state (the less positive voltage) X = state immaterial Z = high impedance state FAMILY DATA, IDD LIMITS category MSI See Family Specifications Sn X L H L Rn X H X L OUTPUT On Z L H latched Fig.1 Functional diagram. January 1995 2 Philips Semiconductors Product specification Quadruple R/S latch with 3-state outputs HEF4043B MSI Fig.4 Logic diagram (one latch). Fig.3 Logic diagram. January 1995 3 Philips Semiconductors Product specification Quadruple R/S latch with 3-state outputs AC CHARACTERISTICS VSS = 0 V; Tamb = 25 C; CL = 50 pF; input transition times 20 ns VDD V Propagation delays Rn On HIGH to LOW Sn On LOW to HIGH Output transition times HIGH to LOW LOW to HIGH 3-state propagation delays Output disable times EO On HIGH 5 10 15 5 LOW Output enable times EO On HIGH 5 10 15 5 LOW Minimum Sn pulse width; HIGH Minimum Rn pulse width; HIGH 10 15 5 10 15 5 10 15 tWRH tWSH 30 20 16 30 20 16 tPZL tPZH 25 15 10 40 20 15 15 10 8 15 10 8 50 30 25 80 45 35 ns ns ns ns ns ns ns ns ns ns ns ns 10 15 tPLZ tPHZ 45 20 10 50 20 10 90 35 25 100 40 25 ns ns ns ns ns ns 5 10 15 5 10 15 5 10 15 5 10 15 tTLH tTHL tPLH tPHL 90 35 25 65 25 15 60 30 20 60 30 20 180 70 50 135 50 35 120 60 40 120 60 40 ns ns ns ns ns ns ns ns ns ns ns ns SYMBOL MIN. TYP. MAX. HEF4043B MSI TYPICAL EXTRAPOLATION FORMULA 63 ns + (0,55 ns/pF) CL 24 ns + (0,23 ns/pF) CL 17 ns + (0,16 ns/pF) CL 38 ns + (0,55 ns/pF) CL 14 ns + (0,23 ns/pF) CL 7 ns + (0,16 ns/pF) CL 10 ns + (1,0 ns/pF) CL 9 ns + (0,42 ns/pF) CL 6 ns + (0,28 ns/pF) CL 10 ns + (1,0 ns/pF) CL 9 ns + (0,42 ns/pF) CL 6 ns + (0,28 ns/pF) CL see also waveforms Fig.5 January 1995 4 Philips Semiconductors Product specification Quadruple R/S latch with 3-state outputs HEF4043B MSI VDD V Dynamic power dissipation per package (P) 5 10 15 TYPICAL FORMULA FOR P (W) 1100 fi + (foCL) x VDD2 4400 11 400 fi + (foCL) x VDD2 fi + (foCL) x VDD2 where fi = input freq. (MHz) fo = output freq. (MHz) CL = load capacitance (pF) (foCL) = sum of outputs VDD = supply voltage (V) Fig.5 Waveforms showing minimum Sn and Rn pulse widths. APPLICATION INFORMATION An example of application for the HEF4043B is: * Four-bit storage with output enable January 1995 5 |
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